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cxgbe(4): Updates to the hw and fw headers and config file

Browse Source 
MFC after:	1 week
Sponsored by:	Chelsio Communications
This commit is contained in:
Navdeep Parhar
2026-03-09 11:19:49 -07:00
parent 324d53c26b
commit 1bef5535c1
5 changed files with 154 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sys/dev/cxgbe/common/t4_regs.h
+22 -29
View File
@@ -1465,10 +1465,10 @@
#define A_SGE_INT_ENABLE3 0x1040
#define A_SGE_FL_BUFFER_SIZE0 0x1044
#define S_SIZE 4
#define CXGBE_S_SIZE 4
#define CXGBE_M_SIZE 0xfffffffU
#define V_SIZE(x) ((x) << S_SIZE)
#define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
#define CXGBE_V_SIZE(x) ((x) << S_SIZE)
#define CXGBE_G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
#define S_T6_SIZE 4
#define M_T6_SIZE 0xfffffU
@@ -26578,15 +26578,10 @@
#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
#define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
#define S_CIM_SGE1_PKT_ERR_CODE 8
#define M_CIM_SGE1_PKT_ERR_CODE 0xffU
#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
#define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
#define S_CIM_SGE0_PKT_ERR_CODE 0
#define M_CIM_SGE0_PKT_ERR_CODE 0xffU
#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
#define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
#define S_CIM_SGE_PKT_ERR_CODE 0
#define M_CIM_SGE_PKT_ERR_CODE 0xffU
#define V_CIM_SGE_PKT_ERR_CODE(x) ((x) << S_CIM_SGE_PKT_ERR_CODE)
#define G_CIM_SGE_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE_PKT_ERR_CODE) & M_CIM_SGE_PKT_ERR_CODE)
#define S_CIM_PCIE_PKT_ERR_CODE 8
#define M_CIM_PCIE_PKT_ERR_CODE 0xffU
@@ -60550,17 +60545,15 @@
#define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
#define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
#if 0
#define S_B 16
#define M_B 0xffffU
#define V_B(x) ((x) << S_B)
#define G_B(x) (((x) >> S_B) & M_B)
#endif
#define CXGBE_S_B 16
#define CXGBE_M_B 0xffffU
#define CXGBE_V_B(x) ((x) << CXGBE_S_B)
#define CXGBE_G_B(x) (((x) >> CXGBE_S_B) & CXGBE_M_B)
#define S_A 0
#define M_A 0xffffU
#define V_A(x) ((x) << S_A)
#define G_A(x) (((x) >> S_A) & M_A)
#define CXGBE_S_A 0
#define CXGBE_M_A 0xffffU
#define CXGBE_V_A(x) ((x) << CXGBE_S_A)
#define CXGBE_G_A(x) (((x) >> CXGBE_S_A) & CXGBE_M_A)
#define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
#define A_MAC_PORT_PTP_CFG 0x9ac
@@ -62257,10 +62250,10 @@
#define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
#define S_VLANTAG 0
#define CXGBE_S_VLANTAG 0
#define CXGBE_M_VLANTAG 0xffffU
#define V_VLANTAG(x) ((x) << S_VLANTAG)
#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
#define CXGBE_V_VLANTAG(x) ((x) << CXGBE_S_VLANTAG)
#define CXGBE_G_VLANTAG(x) (((x) >> CXGBE_S_VLANTAG) & CXGBE_M_VLANTAG)
#define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
#define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
@@ -69613,10 +69606,10 @@
#define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
#define F_INIT_ENABLE V_INIT_ENABLE(1U)
#define S_WAIT 16
#define M_WAIT 0xfffU
#define CXGBE_V_WAIT(x) ((x) << S_WAIT)
#define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
#define CXGBE_S_WAIT 16
#define CXGBE_M_WAIT 0xfffU
#define CXGBE_V_WAIT(x) ((x) << CXGBE_S_WAIT)
#define CXGBE_G_WAIT(x) (((x) >> CXGBE_S_WAIT) & CXGBE_M_WAIT)
#define S_EN_MULTI_RANK_SEL 4
#define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
sys/dev/cxgbe/firmware/t4fw_interface.h
+99 -8
View File
@@ -2560,6 +2560,22 @@ struct fw_ri_wr {
__be32 tpt_offset_t10_config;
__be32 r8[2];
} nvmet_init;
struct fw_ri_iscsi_init {
__u8 type;
__u8 dcrc_dis_to_hcrc;
__u8 r4[3];
__u8 qp_caps;
__be16 r5;
__be32 pdid;
__be32 qpid;
__be32 sq_eqid;
__be32 r6;
__be32 scqid;
__be32 rcqid;
__be32 r7[4];
__be32 r8[2];
__be64 r9;
} iscsi_init;
struct fw_ri_fini {
__u8 type;
__u8 r3[7];
@@ -2634,6 +2650,37 @@ struct fw_ri_wr {
#define G_FW_RI_WR_T10_CONFIG(x) \
(((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG)
#define S_FW_RI_WR_DCRC_DIS 7
#define M_FW_RI_WR_DCRC_DIS 0x1
#define V_FW_RI_WR_DCRC_DIS(x) ((x) << S_FW_RI_WR_DCRC_DIS)
#define G_FW_RI_WR_DCRC_DIS(x) \
(((x) >> S_FW_RI_WR_DCRC_DIS) & M_FW_RI_WR_DCRC_DIS)
#define F_FW_RI_WR_DCRC_DIS V_FW_RI_WR_DCRC_DIS(1U)
#define S_FW_RI_WR_HCRC_DIS 6
#define M_FW_RI_WR_HCRC_DIS 0x1
#define V_FW_RI_WR_HCRC_DIS(x) ((x) << S_FW_RI_WR_HCRC_DIS)
#define G_FW_RI_WR_HCRC_DIS(x) \
(((x) >> S_FW_RI_WR_HCRC_DIS) & M_FW_RI_WR_HCRC_DIS)
#define F_FW_RI_WR_HCRC_DIS V_FW_RI_WR_HCRC_DIS(1U)
#define S_FW_RI_WR_PSZ_IDX 4
#define M_FW_RI_WR_PSZ_IDX 0x3
#define V_FW_RI_WR_PSZ_IDX(x) ((x) << S_FW_RI_WR_PSZ_IDX)
#define G_FW_RI_WR_PSZ_IDX(x) \
(((x) >> S_FW_RI_WR_PSZ_IDX) & M_FW_RI_WR_PSZ_IDX)
#define S_FW_RI_WR_DCRC 1
#define M_FW_RI_WR_DCRC 0x1
#define V_FW_RI_WR_DCRC(x) ((x) << S_FW_RI_WR_DCRC)
#define G_FW_RI_WR_DCRC(x) (((x) >> S_FW_RI_WR_DCRC) & M_FW_RI_WR_DCRC)
#define F_FW_RI_WR_DCRC V_FW_RI_WR_DCRC(1U)
#define S_FW_RI_WR_HCRC 0
#define M_FW_RI_WR_HCRC 0x1
#define V_FW_RI_WR_HCRC(x) ((x) << S_FW_RI_WR_HCRC)
#define G_FW_RI_WR_HCRC(x) (((x) >> S_FW_RI_WR_HCRC) & M_FW_RI_WR_HCRC)
#define F_FW_RI_WR_HCRC V_FW_RI_WR_HCRC(1U)
/******************************************************************************
* R o C E V 2 W O R K R E Q U E S T s
@@ -2951,6 +2998,24 @@ struct fw_v2_nvmet_tx_data_wr {
#endif
};
#define S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 20
#define M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 0x1
#define V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \
((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE)
#define G_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \
(((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) & \
M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE)
#define F_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE \
V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(1U)
#define S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 18
#define M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 0x3
#define V_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \
((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE)
#define G_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \
(((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) & \
M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE)
#define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 10
#define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 0x3fffff
#define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \
@@ -4990,6 +5055,16 @@ struct fw_crypto_update_sa_wr {
} key;
};
#define S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 3
#define M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 0x1
#define V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \
((x) << S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER)
#define G_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \
(((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) & \
M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER)
#define F_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER \
V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(1U)
#define S_FW_CRYPTO_UPDATE_SA_WR_SAOP 2
#define M_FW_CRYPTO_UPDATE_SA_WR_SAOP 0x1
#define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \
@@ -8952,24 +9027,40 @@ enum fw_port_type {
FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G BP AN */
FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP AN */
FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP AN */
FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP AN */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/50G/25G/10G/1G, BP AN */
FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G, Spider cable */
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G, Spider cable */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/
FW_PORT_TYPE_BARE_LINK_50G = 23, /* No, 1, 50G */
FW_PORT_TYPE_BARE_LINK_100G = 24, /* No, 2, 100G/50G */
FW_PORT_TYPE_BARE_LINK_200G = 25, /* No, 4, 200G/100G/50G */
FW_PORT_TYPE_SFP56 = 26, /* No, 1, 50G/25G */
FW_PORT_TYPE_QSFP56 = 27, /* No, 4, 200G/100G/50G/25G */
FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */
FW_PORT_TYPE_QSFP56_4_50G = 28, /* No, 1, 50G, Spider cable */
FW_PORT_TYPE_KR_50G = 29, /* No, 1, 50G/25G/10G/1G, BP AN */
FW_PORT_TYPE_KR2_100G = 30, /* No, 2, 100G/50G/25G/10G/1G, BP AN */
FW_PORT_TYPE_KR4_200G = 31, /* No, 4, 200G/100G/40G/50G/25G/10G/1G, BP AN */
FW_PORT_TYPE_QSFP56_2_50G = 32, /* No, 1, 50G, Spider cable */
FW_PORT_TYPE_OSFP = 33, /* No, 8, 400G/200G/100G/50G */
FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */
FW_PORT_TYPE_OSFP_2_200G = 35, /* No, 4, 200G, Spider cable */
FW_PORT_TYPE_QSFPDD_2_200G = 36,/* No, 4, 200G, Spider cable */
FW_PORT_TYPE_KR8_400G = 37, /* No, 8, 400G/200G/100G/50G/40G/25G/10G/1G, BP AN */
FW_PORT_TYPE_QSFP56_2_100G = 38,/* No, 2, 100G, Spider cable */
FW_PORT_TYPE_QSFPDD_4_100G = 39,/* No, 2, 100G, Spider cable */
FW_PORT_TYPE_KR2_50G = 40, /* No, 1, 50G/25G/10G/1G, BP AN */
FW_PORT_TYPE_MAX,
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PORTTYPE32
};
sys/dev/cxgbe/firmware/t7fw_cfg.txt
+11 -8
View File
@@ -175,6 +175,11 @@
# TPT error.
# Err2uP = 0
# ULP_TX_ACCELERATOR_CTL
reg[0x8f90] = 0x00000015/0x00000015 # Compression block clock gating
# Dedupe clock gating
# Erasure Coding clock gating
#ULP_RX_CTL1
reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3
# ROCE_Invld_Msg_Dis = 3
@@ -201,7 +206,7 @@
# default gc enabled.
# HMA configuration (uncomment following lines to enable HMA)
hma_size = 128 # Size (in MBs) of host memory expected
hma_size = 256 # Size (in MBs) of host memory expected
hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory
#mc[0]=0
@@ -394,8 +399,7 @@
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
#pmask = 0x4 # access to only one port
pmask = 0x1 # access to only one port
pmask = 0x4 # access to only one port
[function "3"]
nvf = 16 # NVF on this function
@@ -407,7 +411,7 @@
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
#pmask = 0x2 # access to only one port
pmask = 0x8 # access to only one port
# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here. For Egress
@@ -421,7 +425,7 @@
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
nethctrl = 224 # NETHCTRL_UNIFIED + NETHCTRL_WD
nethctrl = 288 # NETHCTRL_UNIFIED + NETHCTRL_WD
neq = 252 # NEQ_UNIFIED + NEQ_WD
nqpcq = 12288
nexactf = 40 # NMPSTCAM_UNIFIED
@@ -435,8 +439,7 @@
nserver = 480 # number of server region entries
nhash = 12288 # number of hash region entries
nhpfilter = 64 # number of high priority filter region entries
#protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp, ofld_sendpath
tp_l2t = 3072
tp_ddp = 2
tp_ddp_iscsi = 2
@@ -643,7 +646,7 @@
[fini]
version = 0x1425001d
checksum = 0x3671da3b
checksum = 0x2419f987
# Total resources used by above allocations:
# Virtual Interfaces: 104
sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
+11 -8
View File
@@ -175,6 +175,11 @@
# TPT error.
# Err2uP = 0
# ULP_TX_ACCELERATOR_CTL
reg[0x8f90] = 0x00000015/0x00000015 # Compression block clock gating
# Dedupe clock gating
# Erasure Coding clock gating
#ULP_RX_CTL1
reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3
# ROCE_Invld_Msg_Dis = 3
@@ -201,7 +206,7 @@
# default gc enabled.
# HMA configuration (uncomment following lines to enable HMA)
hma_size = 128 # Size (in MBs) of host memory expected
hma_size = 256 # Size (in MBs) of host memory expected
hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory
#mc[0]=0
@@ -394,8 +399,7 @@
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
#pmask = 0x4 # access to only one port
pmask = 0x1 # access to only one port
pmask = 0x4 # access to only one port
[function "3"]
nvf = 16 # NVF on this function
@@ -407,7 +411,7 @@
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
#pmask = 0x2 # access to only one port
pmask = 0x8 # access to only one port
# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here. For Egress
@@ -421,7 +425,7 @@
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
nethctrl = 224 # NETHCTRL_UNIFIED + NETHCTRL_WD
nethctrl = 288 # NETHCTRL_UNIFIED + NETHCTRL_WD
neq = 252 # NEQ_UNIFIED + NEQ_WD
nqpcq = 12288
nexactf = 40 # NMPSTCAM_UNIFIED
@@ -435,8 +439,7 @@
nserver = 480 # number of server region entries
nhash = 12288 # number of hash region entries
nhpfilter = 64 # number of high priority filter region entries
#protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp, ofld_sendpath
tp_l2t = 3072
tp_ddp = 2
tp_ddp_iscsi = 2
@@ -643,7 +646,7 @@
[fini]
version = 0x1425001d
checksum = 0x96513217
checksum = 0x83f95163
# Total resources used by above allocations:
# Virtual Interfaces: 104
sys/dev/cxgbe/t4_main.c
+11 -4
View File
@@ -3760,10 +3760,17 @@ port_mword(struct port_info *pi, uint32_t speed)
return (IFM_NONE);
}
break;
case M_FW_PORT_CMD_PTYPE: /* FW_PORT_TYPE_NONE for old firmware */
if (chip_id(pi->adapter) >= CHELSIO_T7)
return (IFM_UNKNOWN);
/* fall through */
case FW_PORT_TYPE_KR4_200G: {
/*
* Pre-T7 firmware used M_FW_PORT_CMD_PTYPE for PORT_TYPE_NONE
* and driver needs to deal with both.
*/
_Static_assert(M_FW_PORT_CMD_PTYPE == FW_PORT_TYPE_KR4_200G,
"driver/firmware mismatch");
if (chip_id(pi->adapter) < CHELSIO_T7)
return (IFM_NONE);
return (IFM_200G_KR4_PAM4);
}
case FW_PORT_TYPE_NONE:
return (IFM_NONE);
}